EasylogicECO Datasheet


Automatic RTL-Based ECO Design Flow Optimized for Best Patch Size and Turnaround Time



EasylogicECO utilizes an innovative functional ECO algorithm to efficiently complete ECO tasks and reduce project cycle delays.  It makes minimal modifications to the original gate-level netlist based on the user's RTL changes, creating a revised netlist that aligns with the updated RTL function.

Solution Benefits


•  RTL-based functional ECO process to preserve the ASIC design flow

•  Short ECO turnaround time for designs of all sizes and complexities

•  Optimized patch for achieving optimal ECO points and minimal gate count, facilitating timing convergence

•  Scan chain fixing and physical-aware delay estimation added for a comprehensive functional ECO process

Introduction to Functional ECO (Engineering Change Order)


Functional ECO (Engineering Change Order) is an incremental design method used to revise existing ASIC designs.  Once an RTL code is revised to change the ASIC function, the ECO process modifies a portion of the existing netlist to align with the revised ASIC function while preserving the integrity of most of the netlist. 


EasylogicECO Design Flow


EasylogicECO seamlessly integrates with the user's existing ASIC design tools, creating a complementary design flow.  Starting with an accurate analysis of RTL behavior changes, the EasylogicECO design process maintains the integrity of RTL flow, avoiding the user's making direct modifications on the gate-level netlist. 

Four major steps in the EasylogicECO flow:


1. User's RTL change

2. Identifying the RTL-level functional changes using any logic equivalence checking tool

3. Generating the reference netlist by synthesizing the Revised RTL

4. Creating an ECO netlist, which includes the original netlist and the ECO patch, and design constraints for downstream operations


EasylogicECO Features

Breakthrough Algorithms for Optimal ECO Results

Utilize patented formal verification algorithms for ECO process to quickly and efficiently complete ECO tasks and obtain optimal results.


Design-For-Test (DFT) Support

Automatic SDFF selection and insertion into the scan chain netlist, perform scan chain stitching and length balancing.  Support advanced design requirements such as low power design and hold time corrections.


Managing ECOs That Create Extensive Impact

Trace ECO impact across the design hierarchy to perform all changes in a single run.  Support large-scale ECO changes caused by instantiations of the same ECO block in multiple environments that leads to an impact on up to tens of thousands of logic cells.


Support for Advanced Design Requirements

Ensure adherence to the original design rules while implementing circuit revisions.  Consider the impac of design changes in DFT, clock domains, and voltage domains during the ECO process and applies necessary adjustments.


Multiple Spare Resources for Post-Mask Tasks

Utilize available physical information to refine logic paths and improve the success rate of the ECO task.  Resource options include standard cells, spare cells, filler cells and logic cells that have been disengaged from the original netlist.  


Automatic End-To-End ECO Design Flow

Support ECO requests raised at any stage of ASIC design, efficiently process ECO changes in a phased sequence to minimize designers’efforts.


Command Line Script Operations

Script-based operations for a simple, easy-to-learn, use, and debug experience.  Provide seamless integrations with mainstream ASIC design flows and support various process nodes. 

Technical Support

For more information, please visit https://www.easylogiceda.com/en/ or email info@easylogiceda.com