Post-Mask ECO

ECO tasks move into Post-Mask scenarios once standard cells, IPs, memories and IOs are placed.  ECO requests could come from a bug found during software validation process, or during testing of the chip sample.  In Post-Mask ECO cases, the RTL changes not only impact all the factors in Pre-Mask ECO, but also limit the solutions to using metal fixes over a limited number of physically available resources such as spare cells.

  • Challenges
  • Solution
  • Tool Features


Challenges Posted by Post-Mask ECO Tasks

Business challenges to overcome

Since it is already late at the post-layout design stage, or at masking stage, or at sample chip testing stage, the success of the ECO task means mitigating the delay of the product release from a few months to a few weeks, while the failure could mean a design re-spin which takes couple of quarters or up to a year. 

Technical challenges to overcome

Metal fixes using filler cells, spare cells or gate array are most critical, and most difficult, in all ECO scenarios.  Limitations of available cells, cell types, cell locations, logic correctness, timing requirements, on top of the scale of functional change itself, really put design team’s engineering creativity to the test. 

Even when logic correctness and timing requirements are achieved, the rule of thumb of Post-Mask ECO is changing as fewer layers in the mask set as possible.  This mostly relies on tool optimization algorithm, trade-off iterations, and the shortest design turnaround time, to identify the result that generates the lowest mask change costs.


Benefits of Easy-Logic solution

Minimizing project delay by short turnaround time

EasylogicECO's patented algorithm streamlines multiple aspects of the ECO process in a signle flow, from revised RTL code to the ECO TCL for layout modifications.  With a focus on total turnaround time, the algorithm delivers accurate results while optimizing efficiency.  Users can set breakpoints to verify the results in each step, or perform the entire ECO flow in a single run, saving users days to weeks of manual iteration.

Simplifying ECO task by physical-aware logic optimization

Advanced physical-aware logic optimization algorithm delivers the shortest path delay by leveraging the user's LEF/DEF information of the existing netlist and spare cells. The ECO job not only covers logic functionality, but also optimizes path timing and ensures patch routability, bridging the gap between netlist ECO and layout ECO.

Reducing the need of user's design expertise

EasylogicECO offers a highly automated flow that requires minimal design knowledge from the user.  Its template-based batch mode execution guides the user through the ECO process and ensures efficient, accurate results without the need for extensive manual intervention. 

Producing the most desirable ECO results

Automated iteration process for identifying optimal ECO points, minimizing patch logic, and optimizing path timing, significantly increases the success rate of functional ECO tasks.


Post-Mask ECO operations encompass the utilization of two distinct types of tool features: physical resource-based implementation optimizations, as well as logic optimizations derived from pre-mask ECO.

1.  Physical optimization features

Improved Layout-aware Optimization Strategy

This capability provides a powerful timing estimation strategy for logic optimization in the ECO process. By utilizing LED/DEF of the original gate-level netlist, it calculates timing estimates based on target cell types and physical locations. This enables more accurate timing optimization, taking into account the layout and physical characteristics of the design. One notable advantage of this capability is that it does not impose limitations on the available cell functions for ECO, making it highly flexible and adaptable to various design scenarios.

Optimization Based on Available Resources in the Vicinity

This capability optimizes the logic function, gate type, and location of available gates by leveraging the surrounding resources in the vicinity. It takes into account the layout constraints, such as LEF and DEF inputs, to optimize the design based on the available resources, resulting in more efficient and optimized placement of gates.

User-Specified Gate Regions

Users have the flexibility to define specific areas in the ECO process for further improvement of the logic optimization results. This includes the ability to define prioritized or restricted regions, allowing users to customize the ECO process based on their design requirements or constraints.

Supported Types of Physical Resources

This capability supports various cell types for post-mask ECO, including spare cell instances, filler cells, and gate arrays. This wide range of supported cell types provides users with ample flexibility to choose the most suitable cell types for their specific design needs.

APR Flow Support

This capability generates layout instructions in both TCL and netlist formats, specifically tailored for APR (Automatic Place and Route) tools, which can be easily integrated into users' preferred APR tool of choice. This streamlines the ECO process and simplifies the generation of optimized layout instructions, making it more efficient and user-friendly.

2.  Logic Optimization Features

Automatic ECO design flow

The ECO flow starts with a functional comparison between the original RTL code and the revised RTL. It is recommended to use the full system module as the input circuit, as it eliminates the need for designers to partition the design and provides a precise understanding of the ECO points. The tool then maps and optimizes the revised circuit based on the available functions of the technology library, leveraging its capabilities to achieve optimal results. Finally, at the output stage, the tool seamlessly integrates the ECO patch with the unchanged portion of the netlist, ensuring a smooth and optimized integration.

Design-For-Test (DFT) Features

This feature restores the DFT functionality in the ECO, specifically focusing on the scan chain portion.  It seamlessly adds/deletes DFFs for newly added/removed registers and creates the required scan chains for the functionally revised circuit while preserving the unchanged scan chains.  The revised scan chain is then stitched to the unchanged portion, creating updated scan chains. Additionally, it offers scan chain balancing and user-defined constraints, empowering users to manipulate the scan chain design to align with their specific design rules. It also ensures that specific test features, such as MBIST cells, are kept intact throughout the ECO process.

ECOs with large extent of impact

The tool automates the search for repetitive changes, feed-through changes, and other modifications throughout the entire design. It performs boundary optimization across hierarchies, allowing for efficient and effective handling of multiple functional ECO changes in a single run.

Special design requirements

In an ECO process, several design requirements must be addressed, which may include ECO across power domains, ECO across clock domains, handling clock-gating and power isolation cells in Low-Power designs, as well as considering Technology libraries for advanced process nodes such as 7nm or 5nm.

Formal verification support

The ECO tool generates references for downstream formal verification, enabling users to convert them into tool constraints for their preferred verification tool. These references contain information related to ECO netlist mapping and optimization.