Scan Chain Fixing

Functional ECO methodology is critical to an ASIC design project, and DFT change is necessary for the success of functional ECO.  Since scan chain logic is automatically generated by EDA tools during the design process, designers often have to put in a great deal of effort on handling scan chain changes to avoid any loss of DFT coverage.

ScanChainECO utilizes an innovative algorithm to assist design teams in efficiently accomplishing scan chain fixing tasks and minimizing test coverage loss resulting from functional ECO.  Based on user’s design changes, ScanChainECO modifies the original scan chain netlist to create a revised netlist that accommodates the updated logic function.  

  • Challenges
  • Solution
  • Tool Features


Challenges posted by Scan Chain Changes


Business challenges to overcome

In today's highly competitive market, test coverage is often a critical requirement in many application segments.  When a functional ECO task adds, or removes, registers in the design, the associated scan chains and test patterns will have to be updated in order to maintain the required test coverage.


Technical challenges to overcome

Since scan chain logic is automatically generated by EDA tools during the design process, designers often have to put in a great deal of effort on handling scan chain changes to avoid any loss of DFT coverage.


Benefits of Easy-Logic solution


Offering short turnaround time for designs of all sizes and complexities

Automatically updates the associated scan chains for the ECO netlist and ensures that various DFT constraints are met, greatly accelerating the ECO turnaround.  Advanced physical-aware logic optimization algorithm delivers the smallest path delay by leveraging the physical information provided of the existing netlist and spare cells. 

A Plug-and-Play tool easily integrated with 3rd-party design flow

Incorporate flow interface features to allow designers using a third-party functional ECO solution to leverage its powerful scan chain fixing capabilities.  The interface utilizes standard data formats and TCL commands, reducing the integration barrier in the flow.

Ease of use and optimized patch for optimal scan chain results

EasylogicECO offers a highly automated flow that requires minimal design knowledge from the user.  Its template-based batch mode execution guides the user through the ECO process and ensures efficient, accurate results without the need for extensive manual intervention. 

SDFF selection and conversion 

Converts regular DFFs into appropriate SDFFs that need to be inserted into the scan chain.

Scan chain stitching, removal and balancing 

Stitches SDFFs into the original scan chain while disconnecting unnecessary SDFFs.  Customizes the chain length based on user’s DFT constraints to meet the requirements of the test plan, enabling increased test coverage without compromising testing costs.

Support for advanced design requirements 

Ensures compliance with design rules while implementing scan chain revisions.  Identifies multi-clock domains, multi-power domains, and hold time violations and applies necessary adjustments, such as isolation/level shifter cells or lockup latches.

Physical-aware ECO algorithm

Utilizes physical information provided in the LEF/DEF format to enhance timing of the scan chain.

Multiple types of post-mask ECO resource

Resource options for a post-mask ECO task include spare cells, gate arrays, and filler cells.  When combined with physical information, optimizes the delay of scan chains by considering cell function and estimated wire delay.

Versatile design flow support

Supports various ECO flows for introducing changes of FFs, including 3rd-party ECO flow, manual ECO flow, and EasylogicECO flow. It utilizes standard formats for input/output data, enabling seamless integration with mainstream design flow.

Command line script operations

Script-based operation is simple, easy to learn and debug.  It only requires modifying specific script fields when migrating to other projects.