Pre-Mask ECO

在设计过程中,如果已经进入到后端物理设计阶段,但是此时RTL代码突然发现需要进行变更(这可能是因为发现了设计错误、或者在进行物理设计时发现某些设计不能满足性能需求需要进行调整、或者客户需求发生了变化、或者使用的第三方IP出现了变更等多种原因),此时如果芯片还没有进行流片,则通过 Pre-Mask ECO 就可以解决。Pre-Mask ECO过程可以对电路布局布线进行修改,可以增加或者删除逻辑单元,灵活性较高。

  • 带来的挑战
  • 解决方案
  • 功能一览表


Pre-Mask ECO 在协助设计团队跟上设计项目进度这一点上提供了巨大的价值。如果RTL 代码更改后不进行ECO,则综合、DFT、P&R等阶段均需要重新完成,这可能使得项目延迟数周甚至数月时间。因此,Pre-Mask ECO可以有效的减少项目延迟,价值巨大。




1. 使用非常简单,自动化程度非常高

     • 针对任何ECO项目均有标准的全自动流程,几乎无需针对不同项目进行特别设定

     • 可以以脚本控制的batch模式执行

2. 最理想的 ECO 结果

     • 工具内部有多种不同算法针对不同的ECO问题均可以得到最优结果

     • 工具有独特的ECO流程可以有效避免生成冗余的补丁逻辑

3. 运算时间短

     • 一次运行即可得到最优结果,无需多次迭代

     • 针对大规模电路的ECO也可以在很短时间内完成


Automatic ECO design flow

The ECO flow starts with a functional comparison between the original RTL code and the revised RTL. It is recommended to use the full system module as the input circuit, as it eliminates the need for designers to partition the design and provides a precise understanding of the ECO points. The tool then maps and optimizes the revised circuit based on the available functions of the technology library, leveraging its capabilities to achieve optimal results. Finally, at the output stage, the tool seamlessly integrates the ECO patch with the unchanged portion of the netlist, ensuring a smooth and optimized integration.

Design-For-Test (DFT) Features

This feature is designed to streamline the DFT functionality in the design, specifically focusing on the scan chain portion.  During the ECO process, it automatically preserves the unchanged scan chain registers while seamlessly adding DFFs for newly added registers or deleting DFFs for removed registers, and create the required scan chains for the functionally revised circuit. The revised scan chain is then stitched to the unchanged portion, creating updated and optimized scan chains. Additionally, it offers scan chain balancing and user-defined constraints, empowering users to manipulate the scan chain design to align with their specific design rules. Furthermore, it ensures that specific test features, such as MBIST cells, are kept intact throughout the ECO process, ensuring their functionality and reliability.

ECOs with large extent of impact

The tool automates the search for repetitive changes, feed-through changes, and other modifications throughout the entire design. It performs boundary optimization across hierarchies, allowing for efficient and effective handling of multiple functional ECO changes in a single run.

Special design requirements

In an ECO process, several design requirements must be addressed, which may include ECO across power domains, ECO across clock domains, handling clock-gating and power isolation cells in Low-Power designs, as well as considering Technology libraries for advanced process nodes such as 7nm or 5nm.

Formal verification support

The ECO tool generates references for downstream formal verification, enabling users to convert them into tool constraints for their preferred verification tool. These references contain information related to ECO netlist mapping and optimization.