Post-Mask ECO

如果芯片已经流片,客户在使用过程中发现功能错误需要修正、或用户需求出现变化希望进行功能变更此时只能通过Post-mask ECO的方式来完成。因为此时芯片已经流片,所以已经不能在电路中增加或删除任意逻辑单元,只能对其中连线进行修改,因此与Pre-mask相比限制更多,对于自动化Functional ECO工具的要求也更加严苛。

  • 带来的挑战
  • 解决方案
  • 功能一览表


在芯片已经流片的情况下,无法再在原有的掩膜版上增加或者删除逻辑单元,此时只能通过Post-mask ECO的方式来修正芯片的逻辑错误。一次Post-mask ECO 任务的成功意味着无需再重新流片即可实现正确功能,对于一个高端芯片(如22nm)可能节省高达千万人民币的重新流片成本。



在Post-mask ECO的情况下,只能使用芯片已经预留的备用单元,无法再额外新增逻辑单元,因此,如何使用最合适的备用单元,保证ECO后的芯片在逻辑功能上可以正确、并且物理性能上也可以满足要求是最关键的。

在实现了逻辑正确性和满足了物理性能约束的同时,Post-Mask ECO 也希望尽可能减少mask改变的金属层数。越少的金属层改变,post-mask ECO的成本也就越低。而这主要依赖于工具算法是否足够优秀能够得到尽量小的补丁逻辑。


1. 使用非常简单,自动化程度非常高

     • 针对任何ECO项目均有标准的全自动流程,几乎无需针对不同项目进行特别设定

     • 可以以脚本控制的batch模式执行

2. 最理想的 ECO 结果

     • 工具内部有多种不同算法针对不同的ECO问题均可以得到最优结果,使得补丁逻辑尽量少,从而可能影响到的金属层数也尽量少

     • 工具有独特的ECO流程可以有效避免生成冗余的补丁逻辑

3. 运算时间短

     • 一次运行即可得到最优结果,无需多次迭代

     • 针对大规模电路的ECO也可以在很短时间内完成

Post-Mask ECO operations encompass the utilization of two distinct types of tool features: physical resource-based implementation optimizations, as well as logic optimizations derived from pre-mask ECO.

1.  物理优化功能

Improved Layout-aware Optimization Strategy

This capability provides a powerful timing estimation strategy for logic optimization in the ECO process. By utilizing LED/DEF of the original gate-level netlist, it calculates timing estimates based on target cell types and physical locations. This enables more accurate timing optimization, taking into account the layout and physical characteristics of the design. One notable advantage of this capability is that it does not impose limitations on the available cell functions for ECO, making it highly flexible and adaptable to various design scenarios.

Optimization Based on Available Resources in the Vicinity

This capability optimizes the logic function, gate type, and location of available gates by leveraging the surrounding resources in the vicinity. It takes into account the layout constraints, such as LEF and DEF inputs, to optimize the design based on the available resources, resulting in more efficient and optimized placement of gates.

User-Specified Gate Regions

Users have the flexibility to define specific areas in the ECO process for further improvement of the logic optimization results. This includes the ability to define prioritized or restricted regions, allowing users to customize the ECO process based on their design requirements or constraints.

Supported Types of Physical Resources

This capability supports various cell types for post-mask ECO, including spare cell instances, filler cells, and gate arrays. This wide range of supported cell types provides users with ample flexibility to choose the most suitable cell types for their specific design needs.

APR Flow Support

This capability generates layout instructions in both TCL and netlist formats, specifically tailored for APR (Automatic Place and Route) tools, which can be easily integrated into users' preferred APR tool of choice. This streamlines the ECO process and simplifies the generation of optimized layout instructions, making it more efficient and user-friendly.

2. 逻辑优化功能

Automatic ECO design flow

The ECO flow starts with a functional comparison between the original RTL code and the revised RTL. It is recommended to use the full system module as the input circuit, as it eliminates the need for designers to partition the design and provides a precise understanding of the ECO points. The tool then maps and optimizes the revised circuit based on the available functions of the technology library, leveraging its capabilities to achieve optimal results. Finally, at the output stage, the tool seamlessly integrates the ECO patch with the unchanged portion of the netlist, ensuring a smooth and optimized integration.

Design-For-Test (DFT) Features

This feature is designed to streamline the DFT functionality in the design, specifically focusing on the scan chain portion.  During the ECO process, it automatically preserves the unchanged scan chain registers while seamlessly adding DFFs for newly added registers or deleting DFFs for removed registers, and create the required scan chains for the functionally revised circuit. The revised scan chain is then stitched to the unchanged portion, creating updated and optimized scan chains. Additionally, it offers scan chain balancing and user-defined constraints, empowering users to manipulate the scan chain design to align with their specific design rules. Furthermore, it ensures that specific test features, such as MBIST cells, are kept intact throughout the ECO process, ensuring their functionality and reliability.

ECOs with large extent of impact

The tool automates the search for repetitive changes, feed-through changes, and other modifications throughout the entire design. It performs boundary optimization across hierarchies, allowing for efficient and effective handling of multiple functional ECO changes in a single run.

Special design requirements

In an ECO process, several design requirements must be addressed, which may include ECO across power domains, ECO across clock domains, handling clock-gating and power isolation cells in Low-Power designs, as well as considering Technology libraries for advanced process nodes such as 7nm or 5nm.

Formal verification support

The ECO tool generates references for downstream formal verification, enabling users to convert them into tool constraints for their preferred verification tool. These references contain information related to ECO netlist mapping and optimization.